1. Field of the Invention
The present invention relates to a boosting circuit that performs an appropriate boosting operation in accordance with load capacitance.
2. Description of the Related Art
In a non-volatile memory such as an EEPROM to and from which data can be electrically written, read, and erased, it is necessary to apply a high voltage that is greater than a power supply voltage VCC to a selected memory cell at the time of writing or erasing data. A charge pump circuit which boosts an input voltage has been used to generate a desired high voltage.
Generally, for an EEPROM, an erasing or writing operation may be performed by selecting memory cells on a byte-by-byte basis, or by selecting memory cells collectively. When the load capacitance varies depending on the number of memory cells selected, the time taken for a power supply voltage VCC to reach a desired boosted voltage VPP (hereinafter, referred to as “boosted-voltage reach time tVVP”) also varies. In the case of selecting the memory cells on a byte-by-byte basis, the load capacitance is low, resulting in a shorter boosted-voltage reach time tVPP. In contrast, in the case of selecting the memory cells collectively, the load capacitance is high, resulting in a longer boosted-voltage reach time tVPP. If the boosted-voltage reach time tVPP is too short, a high voltage will be applied to the memory cells abruptly, which may accelerate the degradation of the memory cells. In contrast, if the boosted-voltage reach time tVPP is too long, it will not be possible to apply a high voltage to the memory cells for a sufficient period of time, which may lead to incomplete data writing.
In order to solve the above-described problems, the following technique has been proposed (for example, see Patent Document 1). In the boosting circuit disclosed in Patent Document 1, the boosted-voltage reach time tVPP is monitored on a real-time basis, and when the boosted-voltage reach time tVPP is short as compared with the time recorded in advance on a ROM, the clock amplitude is decreased to reduce the boosting capability of a charge pump circuit, to thereby adjust the boosted-voltage reach time tVPP so as not to be short. In this manner, the boosted-voltage reach time tVPP is prevented from becoming too short when the load capacitance is low, thereby realizing a boosting operation in an appropriate boosted-voltage reach time tVPP in accordance with the load capacitance.    [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-117773